1. Field of the Invention
The present invention relates to a semiconductor device and in particular to a semiconductor device having a voltage regulator and a protection circuit formed therein.
2. Description of the Related Art
There is known a semiconductor device having an internal circuit and a voltage regulator, in which the voltage regulator generates an internal power supply voltage lower than a power supply voltage supplied via a power supply terminal and then, the internal circuit operates under the internal power supply voltage. Further, there is also known another semiconductor device having such a voltage regulator and an electrostatic discharge protection circuit (referred to as an ESD protection circuit hereinafter). The ESD protection circuit is operative so as to prevent that the internal circuit is applied with a high voltage via the power supply terminal, wherein the high voltage is caused by an electrostatic discharge (referred to as an ESD hereinafter) occurring outside of the semiconductor device (See Japanese Patent Application Kokai No. 2010-3982, for example).
The particular ESD protection circuit protects the internal circuit against the high voltage value caused by the ESD by such an arrangement that a power supply line used for the internal power supply voltage and a grounding line are forced to be connected to each other when the power supply line becomes in a state that the high voltage value is equal to or more than a predetermined voltage value in a relatively short steep rising time (protecting function).
There is however a possibility that the protecting function does not work in case that the voltage regulator operates incorrectly due to the influence of external noise and then outputs an internal power supply voltage higher than the withstanding voltage of the internal circuit. When, for example, the voltage regulator including an output transistor of P-channel MOS (metal-oxide-semiconductor) type transistor is subjected to the influence of external noise resulting in decreasing the gate voltage of the output transistor, then the internal power supply voltage increases. The increase of the internal power supply voltage due to such decrease of the gate voltage of the output transistor is gradual less than the voltage increment due to an ESD. Therefore the protecting function may not occur.